Apparatuses, systems, and methods for direct refresh management sampling protection

ABSTRACT

Apparatuses, systems, and methods for direct refresh management (DRFM) sampling protection. A memory receives a DRFM address and DRFM sampling command from a controller. The memory also samples addresses into an aggressor register. Responsive to receiving the DRFM address, the memory may prevent addresses which match the DRFM address from being added to the aggressor register for at least a period of time. For example, a protect flag may be activated for the period of time. If the aggressor register already contained an address which matched the DRFM address, it may be removed.

BACKGROUND

This disclosure relates generally to semiconductor devices, and morespecifically to semiconductor memory devices. In particular, thedisclosure relates to volatile memory, such as dynamic random accessmemory (DRAM). Information may be stored on individual memory cells ofthe memory as a physical signal (e.g., a charge on a capacitiveelement). The memory may be a volatile memory, and the physical signalmay decay over time (which may degrade or destroy the information storedin the memory cells). It may be necessary to periodically refresh theinformation in the memory cells by, for example, rewriting theinformation to restore the physical signal to an initial value.

Different memory cells may lose information at different rates (e.g.,different rates of memory decay). The memory may perform CBR operationsby refreshing the wordlines in a sequence such that each word line isrefreshed faster than the anticipated rate of information decay. Certainsituations, such as certain access patterns, may cause an increased rateof data decay. To account for this, the memory and/or a controller ofthe memory may identify row addresses which should be refreshed out ofsequence as part of a targeted refresh operation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a semiconductor device according anembodiment of the disclosure.

FIG. 2 is a block diagram of a memory system according to someembodiments of the present disclosure.

FIG. 3 is a block diagram of a refresh control circuit according to someembodiments of the present disclosure.

FIG. 4 is a timing diagram of signals related to refresh operations in amemory according to some embodiments of the present disclosure.

FIG. 5 is a flow chart of a method according to some embodiments of thepresent disclosure.

DETAILED DESCRIPTION

The following description of certain embodiments is merely exemplary innature and is in no way intended to limit the scope of the disclosure orits applications or uses. In the following detailed description ofembodiments of the present systems and methods, reference is made to theaccompanying drawings which form a part hereof, and which are shown byway of illustration specific embodiments in which the described systemsand methods may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practicepresently disclosed systems and methods, and it is to be understood thatother embodiments may be utilized and that structural and logicalchanges may be made without departing from the spirit and scope of thedisclosure. Moreover, for the purpose of clarity, detailed descriptionsof certain features will not be discussed when they would be apparent tothose with skill in the art so as not to obscure the description ofembodiments of the disclosure. The following detailed description istherefore not to be taken in a limiting sense, and the scope of thedisclosure is defined only by the appended claims.

Information in a volatile memory device may be stored in memory cells(e.g., as a charge on a capacitive element), and may decay over time.The memory cells may be organized into rows (wordlines) and columns (bitlines), in each bank of a memory array. The memory cells may berefreshed on a row-by-row basis. In order to prevent information frombeing lost or corrupted due to this decay, the memory may carry outrefresh operations, such as auto-refresh or self-refresh operations,which may perform a sequence of CBR refreshes. During a refreshoperation, information may be rewritten to memory cells associated withthe wordline to restore their initial states. The CBR operations may beperformed on the wordlines of the memory in a sequence such that over arefresh cycle all word lines are refreshed.

The rate at which the refresh operations are performed may be chosen toprevent the loss of information, ideally such that each memory cell isrefreshed before the information stored in that memory cell is lost. Therate at which the refresh cycle is performed may be based on an expectedfastest rate of information decay. However, certain access patterns torows of the memory (aggressor rows or aggressor word lines) may cause anincreased rate of decay in the memory cells along nearby rows (victimrows or victim word lines). It may thus be important to identify theseaggressor rows so that their associated victims may be refreshed as partof a targeted refresh operation outside of the normal CBR sequence.

The memory may include logic which controls the timing of targetedrefresh operations. For example, the memory may identify aggressors,store them in an aggressor register, and perform a targeted refreshoperation on addresses (e.g., victim addresses) based on one or moreaddresses in the aggressor register. For example, the memory may performa targeted refresh operation on addresses based on an address in theaggressor register every N CBR operations. The memory may also perform atargeted refresh operation when commanded to by a controller as part ofa refresh management (RFM) command. For example, the memory may receivean RFM command and perform one or more targeted refresh operations basedon aggressor addresses in the aggressor register. The memory may alsoreceive a direct RFM (DRFM) command, which both specifies that thememory should perform a targeted refresh operation, and also specifiesthe aggressor address and the range of victim word lines which should berefreshed as part of the targeted refresh operation. However, if thememory identifies an address as an aggressor and also receives the sameaddress via a DRFM command, then the victims of that address may be overrefreshed, and may, in extreme cases become aggressors themselves. Itmay therefore be useful to prevent addresses received as part of DRFMoperations from over-refreshing (of their victims).

The present disclosure is drawn to direct refresh management samplingprotection. A memory receives a DRFM address as part of a DRFMoperation. For example, the controller may provide an address as well asa DRFM sampling command. The memory may prevent the DRFM address frombeing refreshed as part of a non-DRFM targeted refresh operation for atleast a period of time after the DRFM address was received. For example,the DRFM address may be compared to the addresses already in theaggressor register. If there is not a match (e.g., the DRFM address isnot in the aggressor register), then the DRFM address may be preventedfrom being added to the aggressor register for at least a set period oftime. If the DRFM address was already in the aggressor register, thenthe matching address in the aggressor register may be cleared, and theDRFM address may be prevented from being added again to the aggressorregister for at least a set period of time. This may prevent the memoryfrom performing a non-DRFM targeted refresh operation on the DRFMaddress for at least the set period of time.

FIG. 1 is a block diagram of a semiconductor device according anembodiment of the disclosure. The semiconductor device 100 may be asemiconductor memory device, such as a DRAM device integrated on asingle semiconductor chip.

The semiconductor device 100 includes a memory array 118. The memoryarray 118 is shown as including a plurality of memory banks. In theembodiment of FIG. 1 , the memory array 118 is shown as including eightmemory banks BANK0-BANK7. More or fewer banks may be included in thememory array 118 of other embodiments. For example, memories may include4, 16, 32 more or fewer banks. Each memory bank includes a plurality ofword lines WL, a plurality of bit lines BL and/BL, and a plurality ofmemory cells MC arranged at intersections of the plurality of word linesWL and the plurality of bit lines BL and/BL. The selection of the wordline WL is performed by a row decoder 108 and the selection of the bitlines BL and/BL is performed by a column decoder 110. In the embodimentof FIG. 1 , the row decoder 108 includes a respective row decoder foreach memory bank and the column decoder 110 includes a respective columndecoder for each memory bank. The bit lines BL and/BL are coupled to arespective sense amplifier (SAMP). Read data from the bit line BL or/BLis amplified by the sense amplifier SAMP, and transferred to read/writeamplifiers 120 over complementary local data lines (LIOT/B), transfergate (TG), and complementary main data lines (MIOT/B). Conversely, writedata outputted from the read/write amplifiers 120 is transferred to thesense amplifier SAMP over the complementary main data lines MIOT/B, thetransfer gate TG, and the complementary local data lines LIOT/B, andwritten in the memory cell MC coupled to the bit line BL or/BL.

The semiconductor device 100 may employ a plurality of externalterminals that include command and address (C/A) terminals coupled to acommand and address bus to receive commands and addresses, and a CSsignal, clock terminals to receive clocks CK and/CK, data terminals DQto provide data, and power supply terminals to receive power supplypotentials VDD, VSS, VDDQ, and VSSQ. The external terminals may becoupled to a controller (not shown in FIG. 1 ) which may operate thememory by providing various signals to the external terminals.

The clock terminals are supplied with external clocks CK and/CK that areprovided to an input circuit 112. The external clocks may becomplementary. The input circuit 112 generates an internal clock ICLKbased on the CK and/CK clocks. The ICLK clock is provided to the commanddecoder 106 and to an internal clock generator 114. The internal clockgenerator 114 provides various internal clocks LCLK based on the ICLKclock. The LCLK clocks may be used for timing operation of variousinternal circuits. The internal data clocks LCLK are provided to theinput/output circuit 122 to time operation of circuits included in theinput/output circuit 122, for example, to data receivers to time thereceipt of write data.

The C/A terminals may be supplied with memory addresses. The memoryaddresses supplied to the C/A terminals are transferred, via acommand/address input circuit 102, to an address decoder 104. Theaddress decoder 104 receives the address and supplies a decoded rowaddress XADD to the row decoder 108 and supplies a decoded columnaddress YADD to the column decoder 110. The address decoder 104 may alsosupply a decoded bank address BADD, which may indicate the bank of thememory array 118 containing the decoded row address XADD and columnaddress YADD. The C/A terminals may be supplied with commands. Examplesof commands include timing commands for controlling the timing ofvarious operations, access commands for accessing the memory, such asread commands for performing read operations and write commands forperforming write operations, as well as other commands and operations.The access commands may be associated with one or more row address XADD,column address YADD, and bank address BADD to indicate the memorycell(s) to be accessed.

The commands may be provided as internal command signals to a commanddecoder 106 via the command/address input circuit 102. The commanddecoder 106 includes circuits to decode the internal command signals togenerate various internal signals and commands for performingoperations. For example, the command decoder 106 may provide a rowcommand signal to select a word line and a column command signal toselect a bit line. The command decoder 106 also provides activation andpre-charge signals to the different banks of the memory. An activationsignal ACT may indicate that a word line in that bank should beactivated, while a pre-charge signal Pre may indicate that the wordlines should be pre-charged (e.g., closed) in anticipation of a nextactivation command. In some embodiments, the ACT and Pre signals mayshare a signal line.

The device 100 may receive commands and addresses as part of an accessoperation such as a read operation. As part of the access operation, arow address and bank address received along with an activate command. Aspart of the access operation, a column address and bank address arereceived along with a read command. Responsive to the read operation,read data is read from memory cells in the memory array 118corresponding to the row address and column address. The commandsassociated with the read operation are received by the command decoder106, which provides internal commands so that read data from the memoryarray 118 is provided to the read/write amplifiers 120. Responsive tothe activate command the row decoder 108 activates a word lineassociated with the row address. While the row is active, memory cellsalong that row are coupled to sense amplifiers activated by the columndecoder 110 responsive to the read command to read data out along theLIOT/B lines. The read data is output to outside from the data terminalsDQ via the input/output circuit 122. The command decoder 106 may thenprovide a pre-charge command which may ‘close’ the active row.

The device 100 may receive commands and addresses as part of an accessoperation such as a write operation. As part of the write operation, arow address and bank address are received along with an activatedcommand and a column address and bank address are received along withwrite data and a write command. Responsive to the write operation, writedata supplied to the data terminals DQ is written to a memory cells inthe memory array 118 corresponding to the row address and columnaddress. The commands associated with the write operation are receivedby the command decoder 106, which provides internal commands so that thewrite data is received by data receivers in the input/output circuit122. Responsive to the activate command the row decoder 108 activates aword line associated with the row address. While the row is active,memory cells along that row are coupled to sense amplifiers activated bythe column decoder 110 responsive to the write command to receive writedata. Write clocks may also be provided to the external clock terminalsfor timing the receipt of the write data by the data receivers of theinput/output circuit 122. The write data is supplied via theinput/output circuit 122 to the read/write amplifiers 120, and by theread/write amplifiers 120 to the memory array 118 to be written into thememory cell MC. The command decoder 106 may then provide a pre-chargecommand which may ‘close’ the active row.

The device 100 may also perform refresh operations, such as CBR refreshoperations. The CBR refresh operations may be performed as part of anauto-refresh operation, where a controller issues an auto-refreshcommand or as part of a self-refresh operation, where the memoryrefreshes itself based on internal commands. For example, in someembodiments, the auto-refresh mode command may be externally issued tothe memory device 100. In some embodiments, the self-refresh modecommand may be periodically generated by a component of the device.Whether responsive to an external command (e.g., auto-refresh) orinternal logic (e.g., self-refresh) a refresh signal is used to controltiming of refresh operations. For the sake of brevity, a single refreshsignal AREF is described herein, however in some embodiments separatesignals may be used for auto- and self-refresh.

The refresh signal AREF is supplied to the refresh control circuit 116.The refresh control circuit 116 supplies a refresh row address RXADD tothe row decoder 108, which may refresh one or more wordlines WLindicated by the refresh row address RXADD. In some embodiments, therefresh address RXADD may represent a single wordline. In someembodiments, the refresh address RXADD may represent multiple wordlines,which may be refreshed sequentially or simultaneously by the row decoder108. In some embodiments, the number of wordlines represented by therefresh address RXADD may vary from one refresh address to another. Therefresh control circuit 116 may be controlled to change details of therefreshing address RXADD (e.g., how the refresh address is calculated,the timing of the refresh addresses, the number of wordlines representedby the address), or may operate based on internal logic.

The refresh control circuit 116 may selectively output a targetedrefresh address (e.g., which specifies one or more victim address basedon an aggressor) or an automatic refresh address (e.g., from a sequenceof CBR addresses) as the refresh address RXADD. Based on the type ofrefresh address RXADD (and in some embodiments, one more additionalsignals indicating the type of operation), the row decoder 108 mayperform a targeted refresh or CBR operation. The automatic refreshaddresses may be from a sequence of addresses such that over a cycle ofthe sequence, all of the word lines are refreshed. For example, acounter circuit may be used to increment or otherwise ‘count through’possible row address values for RXADD. The refresh control circuit 116may cycle through the sequence of CBR addresses at a rate determined byAREF. A refresh cycle may represent the CBR address generator refreshingeach row of the memory (e.g., providing each value of the CBR address).In some embodiments, the CBR operations may generally occur with atiming such that the sequence of CBR addresses is cycled such that noinformation is expected to degrade in the time between CBR operationsfor a given wordline. In other words, CBR operations may be performedsuch that each wordline is refreshed at a rate faster than the expectedrate of information decay.

The refresh control circuit 116 may also determine targeted refreshaddresses which are addresses that require refreshing (e.g., victimaddresses corresponding to victim rows) based on the access pattern ofnearby addresses (e.g., aggressor addresses corresponding to aggressorrows) in the memory array 118. The refresh control circuit 116 may useone or more signals of the device 100 to calculate the targeted refreshaddress RXADD. For example, the refresh address RXADD may be acalculated based on the row addresses XADD provided along a row addressbus by the address decoder 104.

The refresh control circuit 116 includes an aggressor detector circuitwhich monitors the row addresses XADD provided as part of accessoperations to determine which rows are aggressors. For example, therefresh control circuit 116 may include an aggressor register, andaddresses may be sampled off the address bus. In some embodiments,addresses may be sampled into the aggressor register with random timing.The refresh control circuit 116 uses the identified aggressors todetermine the refresh addresses RXADD used in targeted refreshoperations. For example, if an address XADD is identified as anaggressor, then the victim addresses issued as RXADD may include XADD+1,XADD−1 (e.g., the physically adjacent word lines), XADD+2, XADD−2,and/or other word lines which are near to the word line associated withXADD.

The refresh control circuit 116 includes internal logic which determineswhen to perform a targeted refresh operation. For example, each timeAREF is received, the refresh control circuit may generate a number of‘refresh pumps’ each associated with a refresh operation. For example,after receiving AREF, the refresh control circuit 116 may provide fourpumps (e.g., four refresh addresses RXADD). More or fewer pumps per AREFmay be used in other examples. In some examples the number of pumps perAREF may vary. The pumps may each specify an CBR or targeted refreshoperations. In some embodiments, each pump group (e.g., the set of pumpsproduced responsive to an AREF) may include a mix of targeted and CBRoperations. In some embodiments, each pump group may include refreshoperations of one type or the other. In some embodiments, the refreshcontrol circuit 116 may perform a set of targeted refresh operationsafter performing some number of CBR operations.

The memory device 100 may receive a refresh management RFM command atthe C/A terminals. The RFM command may instruct the memory device 100 toperform a targeted refresh command even if one was not otherwise calledfor. For example the memory 100 may immediately perform a targetedrefresh operation, or may perform a targeted refresh operation as a nextrefresh operation, even if that refresh would otherwise have been a CBRrefresh operation. Responsive to the RFM command, the refresh controlcircuit 116 may select the aggressor word line (e.g., from a queue ofidentified aggressors) and victims to refresh.

The memory device 100 may receive direct refresh management DRFMcommands (e.g., a DRFM sampling command and a DRFM service command) atthe C/A terminals. The DRFM commands may instruct the memory device 100to perform a targeted refresh command, similar to the RFM command, butunlike the RFM command, the DRFM commands also specify an aggressor wordline to use to calculate the refresh addresses RXADD, and may alsospecify other details such as how those refresh addresses should becalculated. For example, as part of an access operation the memory 100may receive a bank address BADD, row address XADD and activate commandat the C/A terminals and then may subsequently receive the DRFM samplingcommand. Responsive to the DRFM sampling command, the refresh controlcircuit 116 associated with that bank may store the row address RXADD ina DRFM register of the refresh control circuit 116. Responsive to a DRFMservice command, the refresh control circuit 116 may begin issuingrefresh addresses RXADD based on the address stored in the DRFM latch.

When the memory 100 receives a DRFM sampling command along with anaddress (e.g., a DRFM address), the memory 100 may be prevented fromperforming a non-DRFM targeted refresh operation based on aggressoraddresses which match the DRFM address. For example, when a DRFM addressis received, a protect flag may be activated, and while active, noaddress which matches the DRFM address may be loaded into the aggressorregister. If an address which matched the DRFM address was already inthe aggressor register, it may be removed.

The power supply terminals are supplied with power supply potentials VDDand VSS. The power supply potentials VDD and VSS are supplied to aninternal voltage generator circuit 124. The internal voltage generatorcircuit 124 generates various internal potentials VPP, VOD, VARY, VPERI,and the like based on the power supply potentials VDD and VSS suppliedto the power supply terminals. The internal potential VPP is mainly usedin the row decoder 108, the internal potentials VOD and VARY are mainlyused in the sense amplifiers SAMP included in the memory array 118, andthe internal potential VPERI is used in many peripheral circuit blocks.

The power supply terminals are also supplied with power supplypotentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ aresupplied to the input/output circuit 122. The power supply potentialsVDDQ and VSSQ supplied to the power supply terminals may be the samepotentials as the power supply potentials VDD and VSS supplied to thepower supply terminals in an embodiment of the disclosure. The powersupply potentials VDDQ and VSSQ supplied to the power supply terminalsmay be different potentials from the power supply potentials VDD and VSSsupplied to the power supply terminals in another embodiment of thedisclosure. The power supply potentials VDDQ and VSSQ supplied to thepower supply terminals are used for the input/output circuit 122 so thatpower supply noise generated by the input/output circuit 122 does notpropagate to the other circuit blocks.

FIG. 2 is a block diagram of a memory system according to someembodiments of the present disclosure. The system 200 includes acontroller 210 and a memory 220. The memory 220 may, in someembodiments, represent the memory device 100 of FIG. 1 . The memory 220shows a simplified view of components relevant to refresh operations.Some components and signals may be omitted for clarity.

The controller 210 is coupled to the memory 220 by variouscommand/address (C/A) signal lines. Row hammer logic 212 of thecontroller 210 may provide an address XADD and a DRFM command along theC/A lines to the memory 220. The memory 220 includes an address decoder222 and command decoder 224 which process the addresses and commandsrespectively. A refresh control circuit 230 of the memory 220 provides arefresh address RXADD as part of a refresh operation. The refreshcontrol circuit 230 includes an aggressor detector 232, which locatesand stores aggressor addresses HitXADD based on the access patterns torow addresses XADD. A refresh cycle control circuit 234 determines atype of refresh operation, and generates internal refresh signals whichindicate the type of refresh operation. For example, a signal IREF mayindicate a CBR refresh operation, while a signal RHR indicates atargeted refresh operation.

A refresh address generator 238 generates the refresh addresses RXADDbased on internal logic (e.g., a counter) for a CBR refresh operation,generates the RXADD based on an address HitXADD from the aggressordetector 232 for a (non-DRFM) targeted refresh operation, or generatesRXADD based on a DRFM address DRFMXADD from the DRFM logic 236 for aDRFM targeted refresh operation. In some embodiments, since DRFM andnon-DRFM targeted refresh operations may chiefly differ in the source ofthe address used to calculate RXADD, a multiplexer (not shown in FIG. 2) may be used to switch a source of the address between HitXADD andDRFMXADD, but the refresh address generator 238 may respond to them inthe same way.

The refresh control 230 includes DRFM logic 236 which stores an addressXADD as a DRFM address DRFMXADD based on a DRFM sampling commandDRFM_samp provided by the command decoder 224. Once an address has beenloaded in the DRFm logic 236, then the Responsive to a DRFM servicecommand DRFM_serv, the refresh cycle control 234 instructs the refreshaddress generator 238 to generate the addresses RXADD based on DRFMXADD.A multiplexer 229 provides either the original row address XADD (if norefresh operation is called for) or the refresh address RXADD (if therefresh control circuit 234 indicates that a refresh operation is calledfor) to a row decoder 228. The row decoder 228 then refreshes word linesbased on the refresh address(es) RXADD or accesses the row address XADD.

The controller 210 operates the memory 220, for example by providingcommands and addresses along CA signal lines to CA terminals of thememory 220. The controller may provide addresses, such as row addressesXADD, along with commands which cause the memory to perform variousoperations on the memory cells specified by the addresses. For examplethe controller may be a processor associated with the memory 220.

The controller 210 includes row hammer logic 212 which identifiesaggressor addresses and determines if they should be refreshed as partof a DRFM operation or not. For example, the row hammer logic 212 maymonitor addresses XADD which are provided to the memory 220. If a givenaddress is provided a certain number of times and/or above a certainfrequency, it may be identified as an aggressor. For example, the rowhammer logic 212 may count a number of times that addresses are providedand identify the address as an aggressor if the count exceeds athreshold.

If the row hammer logic 212 determines that a DRFM operation is calledfor, it may provide a DRFM sampling command and a DRFM service commandalong a C/A bus to the memory 220 along with the identified aggressoraddress XADD and its bank address BADD. Various sequences of signals andcommands may be used to provide the DRFM sampling and service commandsto the memory 220. For example, the DRFM sampling command may beprovided along with other commands associated with an access operationto the address XADD.

The memory includes an address decoder which receives the address XADDand BADD and provides them to various components such as to refreshcontrol circuit 230 and row decoders 228. There may be a row decoder 228and refresh control circuit 230 for each bank, and the bank address BADDdetermines which row decoder 228 and refresh control circuit 230receives the address XADD. A command decoder 224 receives commands fromthe controller 210, such as the DRFM commands. The aggressor addressXADD and DRFM sampling command may be supplied to the memory 220 alongC/A terminals. For example, in some embodiments, one C/A pin may be setaside to indicate if a DRFM sampling command is provided.

Based on the access commands, the command decoder 224 provides internalsignals such as an activate command ACT (which may open or activate aword line) and a pre-charge command Pre (which may close or pre-chargethe word line). In some embodiments, a single signal line may be usedfor both signals (e.g., a rising edge may indicate ACT and a fallingedge may indicate Pre). The bank address BADD may determine which bankthe signals ACT and/or Pre are provided to.

Responsive to the DRFM sampling command DRFM_samp, the DRFM logic 236may capture (e.g., sample) a current value of the row address XADD. Forexample, the DRFM logic 236 may include a DRFM latch, and responsive tothe signal DRFM_samp, the current value along the row address bus (e.g.,XADD) may be loaded into the DRFM latch as the address DRFMXADD.Responsive to the DRFM sampling command, the DRFM logic 236 may provideDRFM protect signals DRFM_protect, which may include a DRFM protect flagat an active level and the current address DRFMXADD. While the DRFMprotect flag is active, the aggressor detector 232 is prevented fromsampling addresses which match DRFMXADD, and if the aggressor detectoralready stored an address which matches DRFMXADD, it may be removed. TheDRFM logic 236 may keep the DRFM protect flag active for a set period oftime. The time for which the DRFM flag is active may be a setting of thememory such as a fuse setting.

The refresh control circuit 230 includes an aggressor detector 232 whichdetects aggressor addresses based on the addresses XADD along theaddress bus. The aggressor detector 232 may use similar criteria to therow hammer logic 212, such as a number of accesses and/or a frequency ofaccesses to a given address. However, the aggressor detector logic 232may be independent, and may have different criteria. For example, theaggressor detector 232 may use a different threshold for detectingaggressors than the row hammer logic 212.

In an example embodiment, the aggressor detector 232 may sample theaddress XADD off the row address bus responsive to a sampling signalArmSample provided by a sample control circuit 239. The sample controlcircuit 239 may provide the signal ArmSample with random timing,semi-random timing, pseudo-random timing, non-random timing (e.g.,periodic timing), timing based on one or more signals (e.g., ACT),timing based on a clock signal, or combinations thereof. Responsive toan activation of the sampling signal ArmSample, a next value of XADD(e.g., the next access operation after ArmSample) may be sampled andloaded into an aggressor register. If the address was already in theaggressor register, a priority flag may be set. Addresses with thepriority flag set may be provided as HitXADD before addresses in theaggressor register which do not have the priority flag set. When anaddress from the aggressor register is used for a targeted refreshoperation (e.g., it is used by the refresh address generator 238 togenerate addresses RXADD), it may be cleared from the aggressor registerand the flags may be reset.

When the DRFM logic 236 provides the DRFM protect flag at the activelevel, the aggressor detector 232 may compare the address DRFMXADD tothe addresses already stored in the aggressor register. If there is amatch, the address which matches DRFMXADD may be removed from theaggressor register and its priority flags may be reset. While theprotect flag is active, each time a new address is sampled (e.g., eachtime ArmSample is active) the sampled address may be compared toDRFMXADD, and if there is a match, then the sampled address is not addedto the aggressor register.

The refresh control circuit 230 includes a refresh cycle control circuit234 which determines a timing and type of refresh operation. Forexample, the refresh cycle control circuit 234 receives a refresh signalAREF, and generates a set of ‘pumps’ each associated with a refreshoperation. The refresh operations may be CBR operations or targetedrefresh operations. The refresh cycle control circuit 234 may provideinternal signals for each pump to a refresh address generator 238. Basedon the type of refresh operation, the refresh address generator 238provides a refresh address RXADD. For example, if the pump is an CBRoperation, then the refresh address RXADD may be generated from asequence of addresses. For example, the refresh address generator 238may include a counter which increments a current address generate a nextrefresh address RXADD in the sequence. When the refresh address RXADD ispart of a CBR operation (e.g., an CBR address), the address may beassociated with multiple word lines. For example, the address RXADD maybe truncated, and all word lines which have an address which shares thenon-truncated portion in common may be refreshed by the row decoder 228.

When the refresh cycle controller 234 calls for a targeted refreshoperation, the refresh address generator 238 generates the refreshaddress RXADD based on an identified aggressor HitXADD from theaggressor detector 232. For example, the aggressor detector 232 mayinclude a register of identified aggressors and provide them to therefresh address generator 238. The refresh address generator 238 maygenerate refresh addresses RXADD for victim word lines associated withthe aggressor HitXADD. Each aggressor HitXADD may be used to generatemultiple refresh addresses RXADD. For example, refresh addresses RXADDmay be generated for HitXADD+1 and HitXADD−1 (e.g., the adjacent wordlines). Other numbers of victims and relationships between the victimsmay be used (e.g., HitXADD+/−1, +/−2, +/−3, etc.).

The refresh cycle control 234 may use various criteria to determinewhich refresh operations to perform. For example, each time the refreshsignal AREF is received, the refresh cycle control circuit 234 maygenerate four pump signals, each associated with a refresh operation.After a number of CBR operations are performed, a number of targetedrefresh operations are called for. Other patterns of CBR and targetedrefresh operations may be used in other embodiments. In someembodiments, the refresh cycle control circuit 234 may use variouscriteria to alter the rate of auto- and targeted refresh operations.

The controller 210 may provide a refresh management signal RFM.Responsive to the RFM signal, the refresh cycle control circuit 234 mayprovide a set of targeted refresh pumps to the refresh address generator238, even if refresh operations were not otherwise called for. The RFMcommand may cause the refresh control circuit 230 to refresh aggressorsidentified by the aggressor detector 232.

In contrast, responsive to the DRFM command, the refresh control circuit230 refreshes an address provided by the controller 210. The commanddecoder 224 generates a DRFM sampling command DRFM_samp which causes theaddress XADD to be stored in a DRFM logic 236. At some point afterproviding the DRFM sampling command DRFM_samp, the command decoder 224also provides a DRFM service command DRFM_serv. Similar to an RFMcommand, responsive to the DRFM_serv command, the refresh cycle controlcircuit 234 may provide one or more targeted refresh pumps, even ifrefresh operations were not otherwise called for. Refresh addresses aregenerated based on the address DRFMXADD stored in the DRFM logic 236.

In some embodiments, the bank logic may also include fuse logic whichdetermines if the row address XADD has been repaired, and if soredirects the row decoder 228 to access a redundant word line instead ofthe original word line associated with the row address. In someembodiments, the refresh address generator 238 may take redundancyinformation into account to ensure that during a targeted refreshoperation, the victim addresses 238 are associated with word lines whichhave a spatial relationship (e.g., physically adjacent, 2 away, 3 away,etc.) from the word line associated with the address XADD.

FIG. 3 is a block diagram of a refresh control circuit according to someembodiments of the present disclosure. The refresh control circuit 300may, in some embodiments, may implement a portion of the refresh controlcircuit 116 of FIGS. 1 and/or 230 of FIG. 2 . In particular the refreshcontrol circuit 300 shows components relevant to the DRFM protect flag.

The refresh control circuit 300 includes an aggressor detector circuit310 (e.g., 232 of FIG. 2 ) which samples aggressor addresses fornon-DRFM targeted refresh operations, and DRFM logic 320 (e.g., 236 ofFIG. 2 ) which receives a DRFM address DRFMXADD identified by acontroller. The refresh control circuit 300 also includes a multiplexer332 and targeted refresh address calculator 334 (e.g., which may becomponents of refresh address generator 238 of FIG. 2 ).

The aggressor detector circuit 310 includes an aggressor register 312and a controller 314 which operates that register. Responsive to asampling signal ArmSample, the controller 314 compares the address XADDto the addresses already stored in the register 312. If the address isnot in the register 312, it may be added to the register 312. In someembodiments, if there is not an open register, than an oldest address inthe register 312 may be replaced with the newly sampled address. If theaddress is already in the register 312, then a priority flag associatedwith the entry where the address is stored may be set. In someembodiments, there may be multiple priority flags (or a counter or othermechanism for tracking multiple levels) which may be incrementally seteach time the address is sampled. One of the stored addresses in theregister 312 may be provided as the aggressor address HitXADD. Addressesin the register 312 with a set priority flag may be provided beforeaddresses without a set priority flag.

The DRFM logic 320 includes a DRFM register 322 and a timer controlcircuit 324. Responsive to a DRFM sampling command DRFM_samp, theaddress XADD is loaded into the DRFM register 322. When the address isloaded in the register 322 (e.g., responsive to the DRFM samplingcommand DRFM_samp), the DRFM logic 320 may provide a DRFM protect flagProtect_Flag at an active level, along with an address Protect_add,which is the DRFM address. The address Protect_add may continue to beprovided for the period of time (e.g., while the Protect_Flag is active)even after the address DRFMXADD leaves the register 322 (e.g.,responsive to a DRFM service command). The DRFM logic 320 provides theprotect flag Protect_Flag at an active level for a period of time basedon a timer control 324. For example, the timer control 324 may begincounting a number of cycles of a timing signal (e.g., a oscillatorsignal, a clock signal, etc.) responsive to receiving DRFM_Samp. Whenthe count in the timer control 324 reaches a threshold, the protect flagProtect_Flag is reset to an inactive level. The threshold may be basedon a setting tmfzDRFMprotect. In some embodiments, the settingtmfzDRFMprotect may be a fuse setting of the memory.

While the DRFM protect flag Protect_Flag is active, the controller 314may compare the address Protect_add to any sampled address XADD receivedby the controller 314. If there is a match, the controller 314 mayignore the sampled address and not add it to the register 312. Inaddition, when Protect_Flag becomes active, the controller 314 maycompare the addresses in the register 312 to the address Protect_add andremove the address from the register which matches Protect_add (andreset any flags associated with that register). In this way, the addressProtect_add may be prevented from being provided as HitXADD for at leastthe time that Protect_Flag is active.

The multiplexer 332 provides either the address HitXADD from theaggressor register 312 if the DRFM service signal DRFM_serv is inactiveor the address DRFMXADD from the DRFM register 322 if the signalDRFM_serv is active. The targeted refresh address calculator 334generates targeted refresh addresses RXADD based on the address itreceives from the multiplexer 332.

FIG. 4 is a timing diagram of signals related to refresh operations in amemory according to some embodiments of the present disclosure. Thetiming diagram 400 shows various signals which may be used to sampleaddresses and prevent the DRFM address from being sampled into anaggressor detector (e.g., 232 of FIGS. 2 and/or 310 of FIG. 3 ). Thetiming diagram 400 includes a trace for external commands, whichincludes signals such as refresh commands for targeted refresh and CBRoperations RHR and CBR, as well as DRFM sample commands (represented byan upward pointing arrow) and DRFM service command. The timing diagram400 also includes activations of the signal ArmSample, andrepresentative registers CAM0 and CAM1 of an aggressor register (e.g.,312 of FIG. 3 ). For the sake of brevity only two aggressor registersare shown. The timing diagram 400 also shows a DRFM register CAM_DRFM(e.g., 322 of FIG. 3 ) and a protect flag Protect_Flag.

At an initial time t0 both aggressor registers are empty and anactivation of the sampling signal ArmSample causes an address Add_0 tobe added to the first register CAM0. Similarly, at a second activationof ArmSample after t0 adds an address Add_1 to the second aggressorregister CAM1. At a time t1, the memory begins performing refreshoperations, which cause the two registers CAM0 and CAM1 to be emptied astheir victims are refreshed. Subsequent to this, another activation ofArmSample causes an address Add_3 to be added to CAM1.

At a time t2, a DRFM sampling command DRFM_samp is received, whichcauses the address Add_3 to be added to the DRFM register CAM_DRFM.Responsive to this, the protect flag Protect_Flag is activated.Responsive to the protect flag being activated, the DRFM address (e.g.,Add_3) is compared to the address(es) in the registers CAM0 and CAM1.Since the DRFM address matches the address in CAM0, the register CAM0 isemptied. At a time t3, a DRFM service command DRFM_serv is received, andthe CAM_DRFM is emptied since its victims are refreshed. The signalProtect_Flag may remain active and therefore the address Add_3 may stillbe provided (e.g., as Protect_add of FIG. 3 ) for comparison even thoughthe DRFM register is empty. At a time t4, the signal ArmSample isactivated and the address which would normally be sampled is Add_3.Since the protect flag is still active and the address matches theprotect address, the address Add_3 is not added to CAM0 (or CAM1). Anactivation of ArmSample after t4 causes an address Add_4 to be sampledinto CAM0.

At a later time, t5, a DRFM sampling command is received and an addressAdd_5 is loaded into the CAM_DRFM. The Protect_Flag becomes activeagain. This time, the two registers CAM0 and CAM1 are empty, so theregisters do not need to be cleared. Between a time t5 and t6, anactivation of ArmSample causes an address Add_6 to be sampled into CAM0(since Add_6 does not match Add_5 in the CAM_DRFM). At a time t6,ArmSample activates while the address Add_5 is on the address bus.Accordingly, it is blocked from being added to the registers. However ata time after t6, the address Add_7 is sampled into the register CAM1. Ata time t7, the protect flag Protect_Flag becomes inactive (because a setamount of time has passed since t5). At a time after t7, ArmSampleactivates and the address Add_5 is added to CAM0. The address Add_5 mayoverwrite the previous address Add_6, since it was the oldest address inthe register.

FIG. 5 is a flow chart of a method according to some embodiments of thepresent disclosure. The method 500 may in some embodiments beimplemented by one or more of the apparatuses or systems describedherein, such as in FIGS. 1-3 .

The method 500 includes box 510, which describes receiving a DRFMaddress from a controller (e.g., 210 of FIG. 2 ). For example, thememory may receive an address along with a DRFM sampling command (e.g.,DRFM_samp). The DRFM and DRFM sampling command may be received at C/Aterminals of the memory. The method 500 may include storing the addressalong the address bus as the DRFM address into a DRFM latch (e.g., 322of FIG. 3 ) responsive to the DRFM sampling command. The method 500 mayinclude providing the DRFM address (e.g., as Protect_add) and activatinga DRFM protect flag (e.g., Protect_Flag) responsive to receiving theDRFM address (and/or to receiving the DRFM sampling signal).

The method 500 includes box 520, which describes sampling an addressinto an aggressor register (e.g., 312 of FIG. 3 ). For example, themethod 500 may include activating a sampling signal with random timing,semi-random timing, pseudo-random timing, non-random timing (e.g.,periodic timing), timing based on one or more signals (e.g., ACT),timing based on a clock signal, or combinations thereof, and samplingthe address on the address bus responsive to the activation of thesampling signal. A controller (e.g., 314) of the aggressor register maycompare the sampled address to the stored addresses in the aggressorregister. If there is not a match, the sampled address may be added tothe register, replacing an existing entry if there is not room. If thereis a match, then a priority flag associated with the entry storing thataddress may be activated.

The method 500 includes box 530, which describes blocking addresseswhich match the DRFM address from being added to the aggressor registerfor a period of time. For, example, while the protect flag is active,the controller of the aggressor register may compare any sampled addressto the DRFM address (e.g., to Protect_add) and may not add any sampledaddress which matches the DRFM address to the aggressor register. Insome embodiments, method 500 may include comparing the DRFM address tothe already stored addresses, and removing any address (and reset itspriority flag) which matches the DRFM address.

The method 500 may include keeping the protect flag active for theperiod of time. For example, a timer control circuit (e.g., 324 of FIG.3 ) in the DRFM logic may count the period of time (e.g., by counting aclock signal or other periodic signal). For example the method 500 mayinclude activating the protect flag and deactivating the protect flagafter the period of time. The method 500 may include determining theperiod of time based on a fuse setting of the memory.

The method 500 may include generating a refresh address based on theDRFM address and refreshing one or more word lines based on the refreshaddress responsive to a DRFM service command. The method 500 may includegenerating a refresh address based on an address in the aggressorregister and refreshing one or more word lines based on the refreshaddress as part of a (non-DRFM) targeted refresh operation.

While in general the present disclosure refers to determining aggressorand victim wordlines and addresses, it should be understood that as usedherein, an aggressor wordline does not necessarily need to cause datadegradation in neighboring wordlines, and a victim wordline does notnecessarily need to be subject to such degradation. The refresh controlcircuit may use some criteria to judge whether an address is anaggressor address, which may capture potential aggressor addressesrather than definitively determining which addresses are causing datadegradation in nearby victims. For example, the refresh control circuitmay determine potential aggressor addresses based on a pattern ofaccesses to the addresses and this criteria may include some addresseswhich are not aggressors, and miss some addresses which are. Similarly,victim addresses may be determined based on which wordlines are expectedto be effected by aggressors, rather than a definitive determination ofwhich wordlines are undergoing an increased rate of data decay.

As used herein, an activation of a signal may refer to any portion of asignals waveform that a circuit responds to. For example, if a circuitresponds to a rising edge, then a signal switching from a low level to ahigh level may be an activation. One example type of activation is apulse, where a signal switches from a low level to a high level for aperiod of time, and then back to the low level. This may triggercircuits which respond to rising edges, falling edges, and/or signalsbeing at a high logical level. One of skill in the art should understandthat although embodiments may be described with respect to a particulartype of activation used by a particular circuit (e.g., active high),other embodiments may use other types of activation (e.g., active low).

Of course, it is to be appreciated that any one of the examples,embodiments or processes described herein may be combined with one ormore other examples, embodiments and/or processes or be separated and/orperformed amongst separate devices or device portions in accordance withthe present systems, devices and methods.

Finally, the above-discussion is intended to be merely illustrative ofthe present system and should not be construed as limiting the appendedclaims to any particular embodiment or group of embodiments. Thus, whilethe present system has been described in particular detail withreference to exemplary embodiments, it should also be appreciated thatnumerous modifications and alternative embodiments may be devised bythose having ordinary skill in the art without departing from thebroader and intended spirit and scope of the present system as set forthin the claims that follow. Accordingly, the specification and drawingsare to be regarded in an illustrative manner and are not intended tolimit the scope of the appended claims.

What is claimed is:
 1. An apparatus comprising: an aggressor register configured to store a plurality of addresses; direct refresh management (DRFM) logic configured to activate a protect flag responsive to receiving a DRFM address; and a control circuit configured to add a sampled address to the aggressor register and configured to prevent the sampled address from being added to the aggressor register if the protect flag is active and the sampled address matches the DRFM address.
 2. The apparatus of claim 1, wherein the control circuit configured to compare the DRFM address to the stored plurality of addresses and remove a selected one of the stored plurality of addresses which matches the DRFM address when the protect flag becomes active.
 3. The apparatus of claim 1, wherein the DRFM logic is configured to provide the protect flag at an active for a period of time.
 4. The apparatus of claim 3, wherein the period of time is determined based on a fuse setting.
 5. The apparatus of claim 1, further comprising generating a refresh address based on the DRFM address responsive to a DRFM service command.
 6. The apparatus of claim 1, wherein the DRFM logic comprises a DRFM register configured to store the DRFM address responsive to a DRFM sampling signal.
 7. The apparatus of claim 6, wherein the DRFM address and DRFM sampling signal are received from a controller.
 8. An apparatus comprising: an aggressor detector circuit configured to sample addresses; and direct refresh management (DRFM) logic configured to store a DRFM address responsive to a DRFM sampling command, wherein the DRFM logic activates a protect flag for a period of time responsive to receiving the DRFM address, wherein the aggressor detector is prevented from sampling addresses which match the DRFM address while the protect flag is active.
 9. The apparatus of claim 8, wherein the DRFM logic includes a timer control circuit configured to count the period of time after the protect flag is activated and deactivate the protect flag when the period of time has elapsed.
 10. The apparatus of claim 9, wherein the period of time is based on a fuse setting.
 11. The apparatus of claim 8, wherein the aggressor detector circuit comprises an aggressor register configured to store a plurality of stored addresses, and wherein the sampled address is not added to the plurality of stored addresses if it matches the DRFM address while the protect flag is active.
 12. The apparatus of claim 11, wherein responsive to the protect flag becoming active the DRFM address is compared to the plurality of stored addresses and if there is a match between the DRFM and one of the plurality of stored addresses, the one of the plurality of stored addresses is removed from the aggressor register.
 13. The apparatus of claim 8, further comprising a refresh address generator circuit configured to provide a refresh address based on the DRFM address responsive to a DRFM service command.
 14. The apparatus of claim 13, wherein the DRFM service command the DRFM sampling command are received from a controller.
 15. A method comprising: receiving a DRFM address from a controller; sampling addresses into an aggressor register; blocking addresses which match the DRFM address from being added to the aggressor register for a period of time after the DRFM address was received
 16. The method of claim 15, further comprising activating a protect flag responsive to receiving the DRFM address and a DRFM sampling command.
 17. The method of claim 16, further comprising deactivating the flag the period of time after activating the protect flag.
 18. The method of claim 15, further comprising removing a stored address which matches the DRFM address from the aggressor register.
 19. The method of claim 15, further comprising refreshing at least one word line in a memory array based on the DRFM responsive to a DRFM service command.
 20. The method of claim 19, further comprising refreshing at least one word line in the memory array based on an address from the aggressor register as part of a targeted refresh operation. 